1. Field of the Invention
This invention is related to semiconductor integrated logic circuits and more specifically, to semiconductor integrated logic circuits having an internal logical circuit comprising flip-flop circuits whose function can be examined by a scan path test method.
2. Description of the Related Art
Conventionally, on testing a semiconductor integrated logic circuit, test pattern signals are generally input into an external input terminal of the integrated logic circuit to determine whether or not a signal designed as a correct signal is output from an external output terminal of the circuit.
Since semiconductor integrated logic circuits have become increasingly larger, other types of testing methods have been used in which control circuits or testing are circuits incorporated within semiconductor integrated logic circuit. A specified internal logical circuit of the integrated logic circuit can be selectively tested through the corresponding control circuit. For example, many fan-in/fan-out terminals are provided for testing a function of an internal logic circuit of the integrated logic circuit involving outputs signals from the internal circuits are taken out from an external terminal of the integrated circuit by using a previously incoporated control circuit.
For another example, for testing a function of an internal loop circuit of a semiconductor integrated logic circuit, the loop circuit is cut halfway by using a previously incorporated control circuit. An output signal is taken from the resultant partial loop circuit via an external terminal of the integrated logic circuit.
Recently, a scan path test and a compact test methods, shown respectively in FIGS. 1 and 2, have been also used in order to improve the controllability and observability of a semiconductor integrated logic circuit.
In FIG. 1, a semiconductor integrated logic circuit to which is to be tested is illustrated. An internal logic circuit is shown comprising n (n.gtoreq.2) D-type flip-flop circuits (among them, four (4) circuits 77, 78, 79 and 80). There are n selector circuits connected to the respective flip-flop circuits (among them, four (4) circuits 73, 74, 75 and 76 are shown here) and another internal logic circuit 82 comprising other members thereof.
In response to the operation of the selector circuits 73, 74, 75 and 76, the flip-flop circuits 77, 78, 79 and 80 are connected in series or cascade with each other to operate as a shift register or, are connected to the second internal circuit 82 to perform a specified logic operation. The function of the circuits 77, 78, 79 and 80 can be examined by a scan path test method when the circuits 77, 78, 79 and 80 operate as a shift resister. In the circuit shown in FIG. 1, the selector circuits 73, 74, 75 and 76 constitute a testing control circuit for the flip-flop circuits 77, 78, 79 and 80.
The semiconductor integrated logic circuit also has four (4) external terminals 70, 71, 72 and 73 for the flip-flop circuits 77, 78, 79 and 80. The terminal 70 is exclusively for testing the input test control signals fed into the selector circuits 73, 74, 75 and 76 and thus is not used in a normal logical operation. On the other hand, the terminals 71, 72 and 73 are used for both of the normal logic operation and a testing operation. The terminal 71 serves as a data signal input terminal to input data signals into the first-stage flip-flop circuit 77. The terminal 72 serves as a clock signal input terminal for input clock signals fed into respective circuits 77, 78, 79 and 80. The terminal 81 serves as a data signal output terminal to take out output signals from the last-stage flip-flop circuit 80.
The selector circuits 73, 74, 75 and 76 respectively incorporated in the data lines of the flip-flop circuits 77, 78, 79 and 80 are operated simultaneously according to a testing control signal input through the external terminal 70. Then, the circuit 73 selects a path for the data signal input through the data input terminal 71 between the first-stage flip-flop circuit 77 and the internal logic circuit 82. The circuit 74 selects a path for the output signal from the circuit 77 between the second flip-flop circuit 78 and the circuit 82. The circuit 75 selects a path for the output signal from flip-flop circuit 78 between the third-stage flip-flop circuit 79 and the circuit 82. Similarly, the selector circuit 76 selects path for the output signal from the (n-1)th-stage flip-flop circuit (not shown in the figure) between the last-stage (n)th-flip-flop circuit and the circuit 82.
When a testing control signal of a high-level (H) is input into the terminal 70, the selector circuits 73, 74, 75 and 76 select respectively the flip-flop circuit as a path for the signal. As a result, the respective flip-flop circuits 77, 78, 79 and 80 operate as a "shift register" to shift the signal from the terminal 71 sequentially from the first flip-flop circuit 77 toward the last-stage flip-flop circuit 80 in response to a clock signal input into the terminal 72. When a testing control signal of a low-level (L) is input, the selector circuits 73, 74, 75 and 76 select, respectively, the internal logic circuit 82 as the path, so that the flip-flop circuits 77, 78, 79 and 80 perform a normal logical operatiodn intrinsic to the semiconductor integrated logic circuit.
Therefore, on examining, by a scan path test method, the flip-flop circuits 77, 78, 79 and 80 shown in FIG. 1, a high-level (H) testing control signal is inputted through the external terminal 70 to set the operation mode in the "shift register operation mode." When a testing scan signal and a clock signal are input respectively into the terminals 71 and 72, output signals from the circuits 77, 78, 79 and 80 are then outputted sequentially from the terminal 81, thus permitting an easy test of the function of the flip-flop circuits 77, 78, 79 and 80.
To allow the integrated logic circuit to perform its normal logic operation, a low-level (L) testing control signal is input into the terminal 70 to set the operation mode in the "logic operation mode." Then, a data signal and a clock signal for the logic operation are input into the terminals 71 and 72, respectively, and an output data signal is obtained from the terminal 81.
Therefore, the semiconductor integrated logic circuit shown in FIG. 1 requires the external terminal 70 as an exclusive termnal for testing. In addition, though not illustrated in FIG. 1, the integrated logic circuit in FIG. 1 requires another exclusive external terminal or terminals for testing as occasion demands.
FIG. 2 shows the compact test method devised to save labor required for making test patterns. In this method, test patterns are generated randomly in a random pattern generator 90 and the test patterns thus generated are used for testing the function of a semiconductor integrated logic circuit. Such patterns are input into a circuit 91 to be tested. An enormous number of the resultant output signals are compressed by a compression function 92. The data-compressed output signals are then compared with the expectation values 92 obtained by an operation simulation to get a judgement result 94.
Sometimes, the scan path test method shown in FIG. 1 and the compact test method shown in FIG. 2 are not suitable depending upon the functions and/or configurations of circuits to be tested. Therefore, since semiconductor integrated logic circuits have recently become so large, the integrated logic circuit generally tends to be incoporated with a testing circuit or circuits so as to enable a selection of testing methods according to the functions and/or configurations of the internal logic circuits constituting the integrated logic circuit.
When examining the function of the integrated logic circuit which can selectively perform different test methods, various types of control signals are required such as those for selecting testing methods and those for stopping an other function or functions temporarily on testing a specified function, in addition to minimal control signals for testing. Thus there arises a problem because many external terminals exclusively for testing are required for input and/or outut of such control signals, in addition to the external terminals for the normal logic operation of the integrated logic circuit.